1. Field of the Invention
The present invention generally relates to a radio-frequency (RF) switch circuit, a semiconductor device, and a method of manufacturing the semiconductor device, and more particularly, to a radio-frequency switch circuit with a stacked structure having field effect transistors (FETS) connected in series, and a semiconductor device, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, multi-port RF switches (SPNTs: Single Pole N-Through; N being the number of ports) formed with field effect transistors (FETs) have been used for portable telephone terminals or the likes involving carrier signals. Those RF switches are required to characteristically have less harmonic components in relation to the fundamental waves of transmission signals. To reduce harmonic components, the linearity of the ON resistance of each FET in an ON state needs to be improved, and high power durability of each FET in an OFF state is required.
As disclosed in FIG. 1 of Japanese Unexamined Patent Publication No. 8-139014, the technique of connecting FETs in series has been used as a general method for improving the power durability in an OFF state. FIG. 1 shows an example (the prior art) of a SPDT (SP2T) as a RF switch in which five FETs are connected in series. A switch circuit (1)50, a switch circuit (2)60, and a resistor 71 are connected to a RF input terminal 70, and the RF input terminal 70 is grounded via the resistor 71. FETs 51, 52, 53, 54, and 55 of the switch circuit (1)50 have sources and drains connected in series, while the source of the FET 51 is connected to the input terminal 70 and the drain of the FET 55 is connected to an output terminal (1)72. The gates of the five FETs are connected to a control terminal (1)74 via resistors Rgg 58. FETs 61, 62, 63, 64, and 65 of the switch circuit (2)60 are connected in series, while the source of the FET 61 is connected to the input terminal 70 and the drain of the FET 65 is connected to an output terminal (2)76. The gates of the five FETs are connected to a control terminal (2)78 via resistors Rgg 68.
When the switch circuit (1)50 is in an OFF state, a negative voltage is applied to the control terminal (1)74, so that the FETs 51, 52, 53, 54, and 55 are put into an OFF state. Accordingly, the input terminal 70 and the output terminal (1)72 are electrically cut off from each other. When the switch circuit (2)60 is in an ON state, a positive voltage is applied to the control terminal (2)78, and the FETs 61, 62, 63, 64, and 65 are put into an ON state. Accordingly, a RF signal that is input through the input terminal 70 passes through the switch circuit (2)60, and is output to the output terminal (2)76.
FIGS. 2A and 2B show the gate current (Ig)-gate voltage (Vg) characteristics of each FET of the switch circuit in an OFF state, and the drain current (Ids)-drain voltage (Vds) characteristics of each FET of the switch circuit in an ON state.
In FIG. 2A, to increase the power durability in the OFF state, the reverse gate withstand voltage (Vgdo) should preferably be high in relation to the power amplitude of a RF signal (the RF amplitude), and the reverse gate current should preferably be in proximity to zero. When the switch circuit (1)50 is in an OFF state, the RF amplitude to be added to each of the FETs 51, 52, 53, 54, and 55 should ideally be ⅕ of the RF amplitude of an input signal. This is because the FETs are connected in series, and the power applied between the input terminal 70 and the output terminal (1)72 is evenly divided. Ideally, five FETs should be connected in series, so as to obtain power durability five times as large as the power durability of a single FET.
In a RF switch, reducing the insertion loss is also crucial. The insertion loss increases as the ON resistance (Ron) becomes higher. In FIG. 2B, the slope representing Ids-Vds in an ON state should preferably be steep, or Ron should preferably be low. Where FETs are connected in series, however, Ron becomes high, and the insertion loss increases. For example, when the switch circuit (2)60 is in an ON state, Ron of the switch circuit (2)60 is the total sum of Ron of the FETs 61, 62, 63, 64, and 65. As the number of FETs connected in series is increased so as to reduce the harmonic components, the insertion loss increases.
Meanwhile, if the power durability is increased by increasing Vgdo of the FETs forming the RF switch, Ron becomes higher. FIGS. 3 and 4 are schematic views illustrating this problem. In each of the FETs shown in FIGS. 3 and 4, a channel layer 14a and a surface layer 27a or 27b are stacked on a semiconductor substrate 10. A source electrode 30, a gate electrode 32, and a drain electrode 34 are formed on the surface layer 27a or 27b. An n+-region 25 is formed below each of the source electrode 30 and the drain electrode 34. In the FET shown in FIG. 3, a depletion layer 28a is formed on the semiconductor surface. To increase Vgdo of the FET shown in FIG. 3, part of the surface layer 27a is removed, and a gate recess that is formed in the surface layer 27b shown in FIG. 4 is formed. By doing so, the depletion layer 28b becomes closer to the channel layer 14a, and Vgdo can be increased. However, the influence of the depletion layer 28breaches the channel layer 14a, and Ron becomes higher. In this manner, when Vgdo is increased, Ron becomes higher. When the harmonic components of the RF switch are reduced by improving the FETs of the RF switch, the insertion loss increases. In the prior art, it is difficult to reduce both the harmonic components and the insertion loss.